CPU
Written by Harry Fairhead   
Article Index
CPU
The Execute Cycle
The Fetch-Execute Cycle

Execute cycle

At the moment, with only a fetch cycle, running a program amounts to transferring each program word into the instruction register in turn but nothing actually gets done!

The solution is to add the “execute cycle”.

After each fetch cycle the next clock pulse initiates an execution phase.

The usual way of explaining the execute cycle is to say that the instruction is “decoded” and then acted upon.

The trouble with this explanation is that it is once again almost mystical and it brings to mind the image of someone living in the machine that looks at the instruction and then does what it says. This is of course still nonsense! What really happens is as automatic, regular and non-intelligent as every other aspect of the working computer.

Every instruction is composed of a number of parts or fields. Exactly how many and what type depends on the architecture of the processor and can be decided by the hardware designer, but there are usually at least two.

The first part is called the “op code”. This is a simple binary value that specifies what the instruction will do.

Most processors have other registers as well as the program counter and the instruction register and these are generally the subjects of instructions. For historical reasons the first general-purpose register is usually called the A register – the “A” standing for Accumulator – and a typical instruction is to load the A register from some specified memory location. Any additional general-purpose registers are usually called B, C, D and so on.

Each instruction has a unique operation code and this not only serves to identify it but it actually causes the computer to carry out the operation. The way that this happens is that the instruction register has a section corresponding to the fixed location of the op code in the instruction.

In our example, shown in the diagram, the op-code corresponds to the top four bits. Each of the bits in the op-code is connected to some combinatorial logic called the instruction decoder which causes the processor to do whatever the op-code corresponds to.

At this point in most descriptions of the workings of the processor the subject of “how” is glossed over but to dispel the mystery we need to look a little closer.

 

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Op-code

The op-code isn’t just any old number;

it has a structure.

In our example the first two bits of the op-code act as a mini address that selects which register the operation is going to use –

11  A register,
10  B register,
01  C register and
00  D register.

The top two bits give the operation to be performed on the register that is selected – e.g.

10 = load the register,
11 = add to the value already in the register
    and so on.

You can see that there is nothing magic in the instruction decoder. The lower two bits are fed into a set of And/Or gates that provide a selection signal to the correct register, i.e. one of the four possible.

The upper two bits are similarly decoded using And/Or gates to derive a signal that makes the register “latch” or load whatever is on the data bus.


The instruction decoder provides signals to select the register and determine what it does

As the processor becomes more complex there are more registers to select from and more operations to set up. However the operation of the instruction decoder is always the same. It picks out parts of the op-code and decodes them to a small number of control lines which change what logic elements are selected or deselected within the CPU.

Address Field

So now you can see that the execute phase works in an entirely automatic way to load the A register, but from where?

The answer is usually that there is a second field in the op-code which is treated as an address. The address portion of the op-code is placed on the address bus at the start of the execute cycle and this determines which memory location the register in question is loaded from or stored to.

fig3 The address field selects a memory address to be used in the operation (click to enlarge)

Notice that what gets placed on the address bus depends on what register is active. During the fetch cycle it is the PC register that is active and it drives the address bus and the instruction register latches what is on the data bus. During the execute cycle it is the instruction register that is active and it drives the address bus and one of the registers latches what is on the data bus.

It really is very simple.

All we need to do now is put it all together.

 

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